The present invention relates to the field of microprocessors comprising an external memory interface (EMI).
An EMI is an intermediate circuit between a data storage memory and a microprocessor that reads and writes the data elements. The EMI type interface has the function of collecting and relaying data transmissions between the microprocessor and the external memory. These are transmissions in the sense of the writing and reading of data elements in the memory.
The prior art architecture, the components of which are also included in the circuit of FIG. 1, includes the two components, the microprocessor MP pnd the memory EM, generally being separate integrated circuits. The interface EMI is preferably implanted in the integrated circuit of the microprocessor MP. The microprocessor itself may be formed by one or more data processing units. It is then possible to distinguish a central processing unit CPU and peripheral units PU1 and PU2. In a known way, the interface EMI is connected by an internal bus of the microprocessor MP to the central processing unit CPU and, as the case may, be to peripheral units PU1 and PU2. The parallel bus enables the high-speed transmission of the data elements that are read or designed to be read in the external memory EM. The data transmission may come, without distinction, from the central processing unit CPU or from peripherals. An arbitration circuit IBA of the internal bus manages the data transmissions on the bus and the transmission requests made by the units CPU, PU1, PU2 or EMI of the microprocessor.
The interface EMI necessarily has buffers INB, OUB because the access to the external memory EM is generally slower than the transmission of data on the internal bus. Furthermore, the internal bus may be requisitioned for other transmissions while the data elements are recorded in the memory EM by the interface EMI.
A buffer INB connected to the internal bus is thus conventionally planned in the interface EMI to receive and store the data elements sent by the microprocessor MP and designed to be recorded in the external memory EM. The interface EMI comprises another buffer OUB also connected to the internal bus, to store and retransmit the data elements loaded from the external memory EM. These data elements are designed to be transmitted to a unit CPU, PU1 or PU2 of the microprocessor MP. The first stage INB which acts in write mode is called the input buffer and the second stage OUB which acts in the read mode is called the output buffer. In the present description, reference shall be made essentially to the input buffer INB.
Furthermore, the interface EMI comprises an external port EXP connected to terminals of the memory EM. The external port EXP connects the data elements during a transfer Trf coming from the input buffer INB or alternately intended for the output buffer OUB. However, the port EXP generally does not have any storage function such as does a buffer.
In the transmission protocols, there are therefore two types of request; loading (reading of the memory) and recording (writing in the memory). The loading or recording requests may come without distinction from the central processing unit CPU or from peripherals. There are simple transmission protocols known in the prior art. In these protocols, the data elements are recorded or loaded one by one, or more specifically, word by word. A data word has a format specified by the standard of the microprocessor, namely 8, 16, 32 or 64 bits . . . (therefore 1, 2, 4 or 8 bytes . . .). The format of the words corresponds to the number of channels of the internal bus of the microprocessor. A loading request simply comprises a data word containing the indication of the order of loading accompanied by address bits of the memory slot to be read. A recording request then comprises two words. The first word contains general indications: recording order bit accompanied by address bits of the memory slot to be selected for the writing. The second word contains the data elements as such, namely the data elements to be written in the selected memory slot.
The EMI interface then carries out requests of this kind as they are received, in processing the first word and temporarily choosing the second word (in the case of writing) in the buffer INB. With this protocol, the interface has a drawback of not being available throughout the performance time of the request. There are known transmission protocols that are more developed. These provide for the loading or recording of a succession of data elements in several successive memory slots. The value of these protocols is that they accelerate the read or write operations of a sequence of data elements. These operations are relatively frequent. Indeed, the access to a memory slot takes place normally in several phases, namely in several clock cycles. A first phase corresponds to the selection of a first part of the memory address, for example the page number, and a second phase corresponds to the selection of a second part of the memory address, such as the row number. The number of phases may increase according to the range of the accessible addresses. When it is sought to access neighboring memory slots, it is possible to omit the re-selection of the part common to the two addresses. Thus, by bringing together the data elements to be recorded or loaded in a single request, the access phases are condensed and the read/write operations are accelerated. The data elements are then combined in packets of data words.
If a recording request concerns four data words, for example as shown in FIG. 3, then the packet Pck comprises five words: a header word Hdr followed by four data words Dat1, Dat2, Dat3 and Dat4. The first word Hdr contains the general information: bits indicating the order of the recording of the packet, accompanied by address bits of the first memory slot that have to be recorded. As above, a load request contains only one data word: bits indicating the loading order accompanied by address bits of the first memory slot that are to be read to form the packet.
There are known microprocessors with external memory interfaces in which the buffer INB can store several packets of words. Thus, a buffer INB having a capacity of ten lines of data elements enables the storage of six words, namely two packets of data elements, assuming that the transmission protocol provides that a packet should comprise five words at most. The utility of increasing the storage capacity of the buffer is that it avoids blocking the microprocessor pending the transcription of a first packet in the memory. However, it must always be planned that the interface EMI will inform the microprocessor MP of the availability status of the buffer INB to prevent another data transmission from being sent to the buffer INB when it is full.
In the known circuits, it is planned that the interface EMI will comprise a counter CPT integrated into the interface control processor ICP. As shown in FIG. 3, the counter CPT accounts for the number of packets stored by the buffer. When the counter CPT indicates that the number of packets stored by the buffer INB has reached the nominal capacity in terms of number of packets, the processor modifies a status signal Rdy given to the arbitration circuit IBA so that this circuit IBA rejects any request for recording of data. In the example of FIG. 3, it is planned that each packet will comprise a maximum of five words and that the buffer will comprise ten lines. As soon as the buffers receives the second packet Pckxe2x80x2, while the first packet Pck is still stored, the counter records the packet number II and the signal Rdy goes to the low state 0. This prevents any other transmission.
One drawback of a microprocessor interface circuit of this kind is that the storage is limited to a nominal number of data packets. Another drawback is that the limitation of the packet storage capacity slows down transmissions between the microprocessor and the external memory. Consecutively, the wait for data transmissions may block the computations of the units of the microprocessor. This has the drawback of reducing the computation speed of the microprocessor.
An object of the invention is to overcome the above-mentioned drawbacks without increasing either the capacity or the amount of space taken up by the buffer. It is an object of the invention to optimize the management of the storage capacity of the buffer and therefore the transmission capacity between the microprocessor and the external memory. In particular, it is an object of the invention to prevent a sub-utilization of the buffer when it stores data packets having a number of words smaller than the maximum get by the protocol.
Another object of the invention is to provide advance information on any future availability of the buffer in order to prepare other data transmissions and organize the arbitration of the transmissions on the bus. Briefly, this object is achieved by providing that the interface will decode each preliminary word of a packet of data words. This decoding relating more specifically to a few bits indicating the format of the packet. These format particulars are used to count up the rows of the buffer occupied by the storage and deduce the availability of the buffer to receive other packets therefrom. This enables the storage of an optimum number of packets. This optimum number may possibly be greater than the nominal number set by the protocol. Furthermore, the decoding of the preliminary word of the packet enables the advance deducing and reporting of the status of future availability of the buffer, namely after the full storage of the packet.
Advantageously, it is planned to carry out a partial early decoding of the format bits before the end of the reception cycle of the preliminary word itself.
The invention is obtained by implementing a method for the control of an external memory interface of a microprocessor. The interface comprising a buffer storing binary data packets transmitted between the microprocessor and the external memory interface, and the buffer having a specified storage capacity of data packets. The method comprising the steps of transmitting data packets between the microprocessor and the interface, storing the data packets in the buffer, computing the capacity of the buffer that is available or unavailable owing to the storage of data packets, and informing the microprocessor of the status of availability or non-availability of the buffer to receive an additional data packet.
The method has the particular feature of decoding format data elements of each data packet, the format data elements being contained in the data packet, and using the decoding of the data packets of each data packet to compute the capacity of the buffer that is available or unavailable owing to the storage of each data packet. This is done to optimize the management of the storage capacity of the buffer and the transmissions between the microprocessor and the interface. A method of this kind is designed especially to be implemented in a microprocessor circuit comprising an interface with an external memory.
Alternatively, the invention is achieved with a microprocessor circuit comprising an external memory interface. The circuit comprises a transmitter for transmitting binary data packets between the microprocessor and the interface. The interface comprising a buffer with a determined capacity storing the transmitted data elements. The circuit also includes a controller capable of computing the capacity of the buffer that is available or unavailable owing to the storage of the data elements and capable of reporting the status of availability of the buffer to receive an additional packet. Additionally, the interface comprises a decoder for decoding format data of a packet, the format data of a packet being contained in the data packet. Each format data decoding operation being given to the controller to optimize the use of the storage capacity of the buffer and the transmission between the microprocessor and the external memory.
Preferably, the decoder is capable of decoding the format data of a packet during the transmission of the packet, the format data of a packet being contained in a preliminary data word of the packet. Preferably, the controller is capable of computing the future capacity of the buffer that will be available or unavailable owing to the storage of the data packet being transmitted and is capable, during the transmission of the packet, of reporting the status of future availability or unavailability of the buffer to receive an additional packet.
According to the preferred embodiment, the decoder is capable of decoding format data elements contained in the preliminary data word during the transmission of the preliminary data word. A preliminary data word containing a few format data bits. According to the preferred embodiment, the controller is capable, during the transmission of the preliminary data word of the data packet, of computing the future capacity of the buffer that will be available or unavailable owing to the storage of the data packet being transmitted. And, the controller is capable, as soon as the transmission of the preliminary data word of the data packet has ended, of reporting the status of future availability or unavailability of the buffer to receive an additional data packet.